This invention relates in general to digital computer systems, and more particularly to a control register in a peripheral chip.
Digital data is represented by binary bits. Microprocessors typically operate on a number of bits of data in parallel. For example, a microprocessor chip may have eight data lines connected to it so that eight binary bits of digital information may be received or transmitted in parallel at any one time.
For communication between a microprocessor and a peripheral device such as a modem, a printer or a data acquisition instrument, it is often expedient for digital data to be carried in a single line connecting between them. In order to do this, the parallel data from the microprocessor must be converted to a serial bit stream for transmission over a cable.
In simpler applications, a "stand-alone" chip commonly known as UART (Universal Asynchronous Receiver/Transmitter) is used to convert digital data between parallel and serial forms.
In more sophisticated applications, a microprocessor-controlled version of the UART is used. It is a software-programmable serial microprocessor peripheral chip (commonly known as USART). The operating mode of a USART is programmable through the bus under the control of a processor. Examples of operating modes options are choices of clock sources, clock rates, choice of asynchronous or synchronous mode, and specification of data encoding format. The controlling parameters are stored in a regular register set residing in the peripheral chip. This regular register set is addressable at any time via normal bus access by the CPU.
While most USART's offer a programmable choice of serial port operating modes, they are generally quite specific about the microprocessors they may be interfaced with, and indeed most CPU (Central Processor Unit) families have their own USART. They also do not offer these same programmable provisions for certain critical hardware parameters of the chip. These hardware parameters control the basic characteristics of the chip and do not change in between hardware resets. For example, by setting the appropriate hardware parameters, the peripheral chip could be put in special test or diagnostic modes. Another hardware parameter may be use to make the chip compatible with either an 8-bit or 16-bit interface. Yet another set of parameters may be used to fine-tune the timing characteristics of the chip.
A few of the peripheral chips do provide a very limited way of selecting between alternative hardware options. One way is to provide for bonding options at the factory level. If two alternative options are desired, the common circuit as well as the two alternative modification circuits are built into the same chip so that the factory has the option of phyically bonding one set or the other to the common circuit as required.
Another way, which provides more flexibility at the user level, is to provide for dedicated pins on chips so that a user can select between the options by programming at the board level by making physical connection from one pin to another.
Yet another way of exercising the various hardware options is to allow for a limited degree of software programmability. Typically, the critical hardware parameters are stored in special registers in the peripheral chip. Unlike the earlier regular type of registers, these special registers cannot be addressed nor set via a normal bus access. Their general inaccessibility helps to insulate against any software errors at run time from affecting the critical hardware parameters. These special registers are normally only settable right after reset. Typically certain pins (a data bus for example) are sampled at the end of the reset cycle, and the controlling parameters are written into the special registers. As the writing of the register is not done with a normal write cycle, dedicated hardware is needed to force the necessary pins to the appropriate values at the end of the reset cycle. This method is cumbersome, and makes the individual programming of more than one peripheral chip impractical.
Accordingly, it is a primary object of the invention to provide an improved method and device which allow the various hardware options of a chip, which are invariant between resets, to be programmably controlled by the content of a control register in the chip and that the control register be addressable and writable through normal bus access, only once after system reset.